Variable delay system for data transfer operations



T. M. HERTZ 3,500,330

VARIABLE DELAY SYSTEM FOR DATA TRANSFER OPERATIONS March 10, 1970 6 Sheets-Sheet 3 Filed Dec. 30, 1966 vast. 04mm INVENTOR THEODORE M. HERTZ ATTORNEY SE53: n 5.6%

March 10, 1970 M HERTZ 3,500,330

VARIABLE DELAY SYSTEM FOR DATA TRANSFER OPERATIONS Filed Dec. 30, 1966 6 Sheets-Sheet 4 M INITIAL MODE 1 Compute sector diiierence T F nnd more in U 111p viops k Determine number of heads to be skipped by counting (in D pairs 0; adjacent binary "Ones in D M SEARCH MODE 1 Search 1'01 address of data to be moved by comparing F with sector track address for agreement;

M READ MODE 1. Begin copying read track into delay Lruck having a number of words delay given by I) and nwnber O1 bibs delay given by D 3 Cl as pr8vcled by shii't reglster D 2 Search 01" ini Lial secLor 01 target. address by comparing T wi Ln sectcr track address M WRITE MODE 1. Copy delay Lrack into write track and count down number 01 sectors L in instruction register until L 0.

FIG. 4

INVENTOR. THEODORE M. HERTZ WE-W ATTORNEY March 10, 1970 T. M. HERTZ 3,500,330

VARIABLE DELAY SYSTEM FOR DATA TRANSFER OPERATIONS Filed Dec. 30, 1966 6 Sheets-Sheet 5 INVENTOR.

THEODORE M HERTZ March 10, 1970 T. M. HERTZ 3,500,330

VARIABLE DELAY SYSTEM FOR DATA TRANSFER OPERATIONS Filed Dec. 30, 1966 6 Sheets-Sheet 6 INVENTOR. THEODORE M HERTZ MW 29. W

ATTORNEY United States Patent 0 3,500,330 VARIABLE DELAY SYSTEM FOR DATA TRANSFER OPERATIONS Theodore M. Hertz, Whittier, Califl, assignor to North American Rockwell Corporation, a corporation of Delaware Filed Dec. 30, 1966, Ser. No. 606,344 Int. Cl. G06f 1/00, 7/00, 15/00; Gllb 13/00 US. Cl. 340-1725 4 Claims ABSTRACT OF THE DISCLOSURE A storage device having a plurality of logically spaced and interconnectable transducers disposed about a storage medium for delaying the transfer of data between non random access storage devices, including logic for determining the transducer interconnections for achieving the required delay.

BACKGROUND OF THE INVENTION Field of the invention The invention relates to a variable delay system for transferring data between non-random access devices using a non-random access intermediate storage device.

Description of prior art Delay systems have been embodied in various configurations for different purposes, for example, Robbins Patent No. 2,674,733 describes delay circuits having a capability for sorting randomly recorded information into an evenly spaced sequence. The delay system is initially set at a maximum delay value under control of a delay control circuit producing the control electrical signals and then is controlled to decrease the delay by a predetermined amount each time a space between the randomly spaced sets of signals is detected. In another patent to Robbins, No. 2,674,732, a sorting and extracting system utilizes a purality of delay sections having delays specified in accordance with a geometric progression which are interconnected by electrical gating circuits. The gating circuits are controlled by binary coded electrical signals representing the desired delay.

Ordinarily, a data transfer system using non-random access storage devices requires transferring data from a storage location in one portion of the system to a different storage location in another portion of the system. In other situations, the interchange of data may be required between one or more data processing systems. However, in either situation, and in other cases where data must be taken from a memory location and transferred after a delay to a different memory location, controls must be included.

Without controls the data could be erroneously written into an incorrect memory location or it could be destroyed because the correct location was not available to receive the data. In certain access systems such as core memories, the difficulty is not present. Addressing means are available for reading from one location to another location without delays usually encountered in a non-random access system such as a disc or drum or delay line memory. In the latter system, time must be lost until the selected location in the memory rotation cycle appears under the writing device which is actuated to place data in that location.

Desirably, means are interposed between the location from which the data is read and the location into which the data is to be written to store the read data until the proper location is available. The storage should include delay means which can be varied between the smallest delay and largest delay possible with the particular system used.

Because of inherent limitations in the location of read and write heads in a non-random access system, the variable delay means should include a means for compensating for the inherent delays resulting from read-write head locations.

The present invention overcomes the problems associated with data transfers between non-random access systems and provides a system which includes the desirable features indicated above.

SUMMARY OF THE INVENTION Briefly, the invention comprises means for determining the difference between the location from which data is transferred and the location which is selected to receive the data and for determining electronic delays which may be incurred in transferring the data. The means for determining electronic delays may be omitted if the transducers can be properly positioned to eliminate the electronic delays.

Further, the invention comprises means for storing data received from the first storage medium in an intermediate storage medium under the control of the delay determining means. The data is stored in the intermediate storage device until the address in the second storage medium selected to receive the data is available. Subsequently, and under the control of the delay determining means, the data is written into the proper location in the receiving storage device.

Therefore, it is an object of this invention to provide a variable delay system for data transferred between 10- cations in non-random access memory devices.

It is another object of this invention to provide an improved system for controlling the transfer of data between non-random access storage devices.

It is a further object of this invention to provide means for determining the time delay to be incurred in transferring data between non-random access storage devices and for storing the data to be transferred for the deter mined delay.

BRIEF DESCRIPTION OF THE DRAWINGS These and other objects of this invention will become more apparent in connection with the following drawings of which,

FIGURE 1 represents an embodiment of a system for transferring data between non-random access memory devices.

FIGURE 2 represents an embodiment of logical circuitry for determining delay and controlling transfer of data.

FIGURE 3 represents an embodiment of means for determining delays to be incurred in transferring data between non-random access memory devices.

FIGURE 4 is a block diagram representation of the various modes comprising system operation.

FIGURE 5a represents logic matrix for determining read/write head interconnection about the delay track.

FIGURE 5b represents the interconnection of read/ write heads with the logic matrix shown in FIGURE 5a.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGURE 1 shows subtractor means 1 for determining the difference between the location from which data is to be read, F and the location into which the data is to be written, T

Difference register 2, connected to subtractor 1, records the calculated difference. Simultaneously, electronic delay counter 3, connected to the difference register, records the delay necessary to compensate for the electronic delays which will be incurred during a transfer. The difference between locations and the recorded delay provides logic control signals for regulating the transfer of data between an address in read track 5 of a non-random access system (not shown) and an address on write track 6 of another non-random access system (not shown).

Although disc memories are illustrated herein as a type of non-random access device, other storage devices such as drum memories and other rotating memories on which a recording surface has been formed, and delay lines, are within the scope of this invention.

Interconnection logic 7 is connected between register 2 and delay track 4 for interconnecting read-write heads of the system in accordance with the difference contained in register 2.

Instruction register 8 is connected to the subtractor, the difference register, and to record counter 9.

Delay register 10 is connected between the read head R of read track 5 and write head W (see FIGURE 3) of the delay track 4. Information, R is gated from track 5 into track 4 through register 10 under the control of delay counter 3. Delay counter 3 provides signals to logic for compensating for the electronic delays. Other embodiments of the control could be achieved between the delay track and the write track.

The transfer operation may be described as a sequence of modes. The mode connections which control the transfer operations are shown by the dotted lines in FIGURE 1. Initial mode logic 11 provides signals to control the instruction register, subtractor, difference register, delay counter and the record counter. The record counter terminates the transfer operation when all the data has been transferred.

Search mode logic 12 is connected to the initial mode logic and becomes actuated at the termination of the initial mode. The search logic determines when the data is to be transferred from track 5.

Read mode logic 13 connected to logic 12, provides signals to control the reading of information from track 5 into track 4. Write mode logic 14 connected between read mode logic 13 and the record counter, controls reading of the information from the delay track into the write track. Inasmuch as there are four modes, the mode control signal could be produced with two switching devices such as flip flops having two logical states.

Sector track 30 is shown as being connected to subtractor 1. It provides sector identification signals for comparing the sector track address with the read track address (F during the search mode and for comparing the sector track address with the write track address (T during the read mode. A portion of the subtractor is used for sector identification in the particular embodiment illustrated. In other embodiments, it may be more practical to use another portion of the system for sector identification or provide a separate identification means. For the particular system described, it is assumed that the sector track is synchronized with the read and write tracks. Synchronization would be possible in the case where the read, write and sector tracks were rotated by a common shaft. In other systems, electronic or mechanical means would have to be provided to synchronize the sector track within the read and write track. Also, it may be more feasible in certain applications to use a substitute for the sector track and sector identification. Suitable substitutes are believed to be well known to those skilled in the art.

Portions of the FIGURE 2 circuitry are designated in the FIGURE 1 system, within the functional blocks comprising the system, so that the functional system representation can be more easily related to the specific structure of FIGURE 2. For example, flip flops D and K designated in the subtractor block are illustrated more specifically in FIGURE 2.

FIGURE 2 shows a specific illustrative embodiment of part of the control electronics generalized in FIGURE 1. Specifically, instruction register 1, connected to the subtractor and the difference register, is shown as comprising a one word recirculating register including write head W and read head R The register temporarily stores information bits representing the track address F from which data is to be extracted and information bits representing the track address T into which the data is to be written. For the system embodiment described, the addresses are represented by six (6) binary digits of computer information.

Binary coded information, L, in one portion of the register, indicates the number of Words to be moved or transferred. Other operational parameters may also be included in the recirculating register.

Subtractor 1 comprises logic 15, including the K borrow flip flop and the D6 flip flop of the difference register. The add-subtract logic subtracts the address F of the read track from the address T of the write track. The difference is inserted into register 2 as a series of logical ones or zeros. Register 2 comprises a shift register in which information is shifted through flip flops D -D Each flip flop, denoted by its subscript, corresponds to an interval of delay, in other words, if the D flip flop contained a binary zero, it would indicate that the delay interval equivalent to D would be omitted. Interconnection logic 7 is connected to register 2 and provides the gating necessary to set the delay in track 4.

Sector read flip flop, R is connected to the K flip flop and provides address information from sector track 30 for comparison with instruction register sector addresses F and T during the search mode and read mode. When there is agreement, the K flip flop provides a sector identification signal which switches from search mode to read mode, to permit the information from the read track to be gated to the delay track. Subsequently, T information is compared with corresponding sector addresses in the sector track 30. When agreement is reached, the K flip flop provides a mode switching signal for gating the information from the delay track into the write. The switching signals are used to switch mode control flip flops M and M The M mode control signal is generated by the M and" gate which provides an input signal to the K comparison flip flop during 1 time. Similarly, an M mode control signal is generated by M and" gate to the comparison flip flop during t time.

Initial mode control gate, M regulates the timing of the difference register during t time. The signal is generated by M and gates.

Information from read head R is gated through the decoding matrix of the delay register under the control of the delay counter.

Delay counter 3 is connected to the difference register and counts a binary one for each pair of ones appearing in flip flops D and D of the difference register. Flip flops g, D and D comprise a binary delay counter. An I signal is provided for clearing the delay counter before a transfer operation begins.

As previously indicated, the spacing between the readwrite heads of a non-random access system may be slightly less than the number of bit positions between the readwrite heads because of inherent electronic delays. As a result, heads properly positioned for a selected interconnection would probably be incorrect for a different interconnection. It is therefore necessary to consider a head to be positioned at least one bit closer to the previous head, opposite to the direction of track rotation, than the power of 2 spacing would indicate. The unit of delay may be more than one bit but it would be the same for each interval between heads. The delays would not be an important consideration if reading from a selected head followed the writing. However, if any heads exist between the read and write operations, the segment or portion of the track between the read and write heads would, in effect, be shortened by the number of positions equal to the number of skipped, or interconnected heads. The skipped heads correspond to the pairs of adjacent binau' ones in the difference register. The pairs of ones are counted by the delay counter, which provides a delay corresponding to the total number of adjacent ones.

Delay counter 3 is connected to delay register through decoding matrix 18. Delay register 10 may be a shift register. Information from the read track is picked up by read head R and shifted into the decoding matrix through flip flops D and D comprising the delay register. The information may go directly into the decoding matrix from R if no delay is required. Mode control and" gate M regulates reading the information from read track into the delay track during t time.

The delay counter provides control signals so that the information is gated through the decoding matrix after a proper delay has been incurred. As previously indicated, the delay could be incurred between the read and delay tracks or between the delay and write tracks.

FIGURE 3 shows read track 5 and read head R for detecting information sorted on the read track. The read head is connected to the delay register so that information passing from the read track can be properly delayed as previously described. The delay register is connected to W, or a particular one of the read-write heads one through six, positioned about delay track 4. Information coming from the delay register is designated as R Delay track 4 is shown as comprising six delay sections. The space between read head 1 and read-write head 2 comprises one space. The other spaces correspond to the intervals between the read-write heads. The heads are spaced so that the bit positions between them correspond to the power of two (2) geometric progression. For example, space between R and Rg/wg is one, or two raised to the zero power. Although six delay sections are shown corresponding to flip flops D through D it is possible to provide more or less delay sections by adding additional heads, or by making the delay track larger. Also, the track can be made smaller and the number of heads reduced.

It should be understood, however, that the number of delay sections corresponds to the number of flip flops comprising the difference register, and the number of flip flops comprising the delay register. The number six was selected because the addresses involved for the described system embodiment are represented by six binary bits.

Write head W, is connected to either read head 1 or a selected one of the read-write heads associated with the delay track. Write head W, writes information at a selected location about write track 6.

The information being transferred is in digital form which is expressed as either a binary 1 or binary 0. The binary l is recorded on the magnetic material comprising the track surface by magnetizing the material in either one of two directions. The recorded information is read by sensing the magnetic orientation as the magnetic surface is passed under a read head.

In other words, if the information were written in by W and read out by R the maximum delay would be achieved. A minimum delay would occur if the information were written directly into track 6 by W Sector track 30 is shown as interconnected, such as by a common shaft, to the read and write tracks. so that the addresses of each track are synchronized. The common shaft is also shown as connecting the read and write tracks with the delay track so that rotation of the tracks is synchronized. The interconnection is shown by the dash lines.

Sector 5 is shown being read by fli flop R The sector addresses are compared by the K flip flop during the M mode. For example, if sector 5 is equal to the address, F during t time and during the M mode, the comparison flip flop generates a signal to switch the mode control flip flop, M for changing the mode. Similarly, a comparison is made during t time of the read mode to regulate transfer of information from the delay track into the write track.

Mode control signals from M, and M regulate reading from the read track into the delay track and from the delay track into the write track. The dash lines show the regulations of the reading from R and writing by W In order to describe the operation of the system, assume that data is to be transferred from sector 5 of P of read track 5 into a sector 60, T and write track 6. In other words, information is read from sector 5 and de layed for S5 sector times until sector 60 appears in position under write head W During the initial mode, M the sector location F is subtracted from sector location T Sector 60 is placed in difference register during t time. During 1 time sector 5 is subtracted. The least significant bit of sector 60 appears in D, at the beginning of 1 time. The least significant bit of sector 5 appearing in R during t time is subtracted from it. If the bits are alike, a zero is written into D as the least significant bit of the difference. If they are not alike, a one is written. If a borrow is indicated, the K flip flop is set. The operation continues until the subtraction is complete and the binary difference, 110111, or 55 in decimal, appears in the difference register. Since D flip flop is zero, logic 7 provides signals to connect W/R and W/R to omit the corresponding delay D indicated in the delay track.

Since the binary number comprises three pairs of adjacent ones, the flip flops comprising the delay counter are set to a binary three. D and D are set to a binary one. D g is set to a binary zero. The read-write interconnection logic interconnects read-write head 5 with read-write head 4 so that sector D is skipped or cut out. Since a maximum of 63 sectors of delay is possible, the 8 sectors of D must be omitted to achieve the desired delay of 55. Information would be read beginning at sector 5 on read track 5, transferred through the delay register in order to take into account the electronic delays, and would be read into W of the delay track. The information then rotates clockwise around the delay track, is read by read-write head 5 and written back onto the delay track by read-write head 4. Subsequently, it is read from the delay track by read head, R and transferred to the write head W; at sector 60 of write track 6. Since 3 pairs of ones appeared in the binary difference, that would indicate that the information being read by R would have to be delayed an additional three bits in going through the delay register so that the actual calculated delay of 55 could be achieved.

If 32 sectors of delay had been calculated, logic 17 would interconnect read-write head 6 with write head W,. In that case, there would be no reason for interconnecting the read-write head, R/W with read head R Also, if a delay of 48 sectors had been calculated, read-write head 5 would be directly connected to W If two sectors of the delay had been indicated by the difference register, information R, coming from the delay register would be connected directly to read-write head 3 and read-write head 2 would then be connected directly to W A more specific illustration of read-write head interconnection logic 7 is seen in FIGURES 5a and 5b. The read head portion of R/W heads 2-6 and R are connected to selected write head portions of the read-write heads or to W, depending on the difference in register 2.

Logic matrices 50 through 55 (FIGURE 5a) interconnect the read-write heads with R; and W For example, R is connected directly to W of the write track if D through D; are set to binary zeros as shown in matrix 50. Information from R is connected to W if D and D are set to binary one and D through D are set to binary zeros as shown in matrix 51. Since information from matrix 51 is only gated into W the line from D of the difference register may be eliminated. The x of the symbolic logic inside the matrix boxes indicates that a line may be eliminated as unnecessary.

In matrix 52 (FIGURE 5a), information R is gated into W if D through D are set to binary zero and D and D are set to binary ones. Since the information is always written into W from matrix 52, it is not necessary to include conductor lines from D and D The same generalization also applies to matrices 53 through 55. Information is always written into W regardless of the logic. Information written in at W, would be written over by the next write head which was actuated by logic 7.

Inputs to the logic matrix are arranged in an order corresponding to the possible inputs to the read-write heads around the delay track going in a clockwise direction as shown in FIGURE b. W can only have input from R because no other read heads separate that head from R W is separated from Rf by R and therefore an input from R must be included. Similarly, since W can have an input from any one of the read-write heads and from R matrix 50 must include inputs from each readwrite head and from R If information is written into W from R there is no need for electrical connections from D; and D to matrix 52 because the information would either have been delayed through those corresponding delay sections or it would have by-passed those delay sections completely before being read by R The matrix also includes write enable inputs W through W The signals are shown although in effect they correspond to the primes of the last difference register bit position input to the matrix as shown in logic described herein.

A more general description of the operation of the system may be seen by referring to the FIGURE 4 mode diagram and the logic of the system for executing each mode.

The mode control diagram is described more fully in connection with FIGURE 4 wherein is shown the four modes comprising system operation.

During the initial mode identified by gate M the sector difference, D is determined in addition to computing the delays incurred due to interconnection of heads.

Sector bits T are copied into the difference register at time by flip flop R as shown by the following logic:

Sector bits, F are subtracted from the T bits during 1 time and the difference is written into the difference register by means of the following logic:

It should be understood that the exact logical interconnections between various flip flops and gates comprising the system as illustrated in FIGURES 1 and 2 are not shown. However, such interconnections are believed well known to such persons skilled in the art and for that reason, full interconnections are not shown.

Borrow logic for the subtractor during the initial mode is,

While the difference between the two locations, D is being inserted into the D register, the number of adjacent binary ones are counted to determine the number of delays which will be incurred as a result of readwrite head interconnections about track 5. The count is recorded in tit the delay counter during t time, by means of the following equations.

The I signal clears the delay counter to zero initially. Time interval, t covers the period the binary difference pairs could appear in the D D flip flops. As a result, 1 time begins two bit times after r time becomes true and turns off one bit time after t; time goes false. Signals may be generated for t through t by flip flops or other means well known to those skilled in the art.

The contents of the instruction register are recircullated and therefore preserved by means of the following logic,

The initial mode, M is terminated after one sector where I is the last bit time of the first sector of the system operation.

Following the initial mode, search mode gate, M is turned on.

During the M mode, as shown in FIGURE 2, the sector bits F in the instruction register are compared through flip flop K with the recorded sector bits of track 30. The K flip flop is turned on so long as no agreement is reached.

Where K,, is false at IL time of the search mode, sector agreement has been reached and the M mode is terminated by,

Subsequently, read mode M begins. Read mode logic may be represented as,

During M data from read track is copied into the delay track in a manner which provides the necessary delay represented by the sector difference D appearing in flip flops D and bit delays corresponding to the contents of the D 4 flip flops. The information read from the read track appears at R and is passed through the five bit shift register D Information read from D is delayed one bit time relative to that read from R information read from D is delayed two bit times, and so on. Possible zero through five bit time delays are covered by the following logic generalized in FIGURE 2 or decoding matrix 18,

Data is written from R into the delay track by a write head determined by the difference register. A write flip flop from logic 7 illustrated in FIGURE 5, actuates a selected R/ W head to generate the bit pattern of ones and zeros for each head. A write enable signal is also provided by logic 7 to enable the flip flop to actuate the 9 R/ W head. Logic for the write flip flops and respective enable signals follows:

After sector agreement is achieved, K will be false at t;, time, which terminates M If the sector difference, D is zero, mode M is skipped In either event, resetting of M initiates the write mode M =M 'M During M data from the delay track is written into the write track starting at T and continuing for as many sector times as indicated by L. Write flip fiop W, and associated write enable signal W have the following logic:

Writing for the correct number of sectors is controlled by a countdown of the value L in the instruction register by one for each sector time until it is reduced below zero as manifested by the carry K remaining true. Record counter 9 of FIGURE 1 is as follows:

where t is the bit time just preceding, and t, is the time during which the value L is read at R Termination of the M mode and the move or transfer instruction results from,

The countdown logic above applies during the one sector time of M as well as M.,,, since both modes contain M This compensates for the additional sector time necessary to reduce the value L below zero.

Also, it should be clear that for records covering more than one track, switching between heads would occur at the track origin (start of sector zero) without loss of time or data.

Although the invention has been described and illustrated in detail, it is to be understoor that the same is by way of illustration and example only, and is not to be taken by way of limitation; the spirit and scope of this invention being limited only by the terms of the appended claims.

I claim: 1. A variable delay system for transferring data from a first non-random access memory device to a second non-random access memory device comprising.

a third non-random access memory device connected between the first and second devices, means for determining the difference between an address in the first memory device and an address in the seocnd memory device, said third device comprises a plurality of delay means for delaying data received from the first device until it is transferred to the second device, including means responsive to said means for determining the difference for by-passing certain of said delay means for achieving a delay equivalent to the determined difference, means interposed between the first device and the second device and responsive to said means for determining for counting electronic delays to be incurred in transferring data from the first device to the third device and for compensating for said delays. 2. A variable delay system for transferring data from a first non-random access memory device to a second non-random access memory deivce comprising,

a third non-random access memory device connected between the first and second devices, means for determining the difference between an address in the first memory device and an address in the second memory device, said third device comprises a plurality of delay means for delaying data received from the first device until it is transferred to the second device, including means responsive to said means for determining the difference for by-passing certain of said delay means for achieving a delay equivalent to the determined difference, said means for determining comprises means for subtracting the addresses and for storing the difference in a binary form comprising logical ones and zeros as the case may be, and means interposed between said first and third devices comprising means for counting adjacent binary ones of said difference and for delaying information from the first device into the third device equivalent to the number of pairs of adjacent ones, each pair of adjacent ones being equivalent to a unit of electronic delay. 3. A variable delay system for transferring data from a first non-random access memory device to a second non-random access memory device comprising,

a third non-random access memory device connected between the first and second devices, means for determining the difference between an address in the first memory device and an address in the second memory device. said third device comprises a plurality of delay means for delaying data received from the first device until it is transferred to the second device, including means responsive to said means for determining the difference for by-passing certain of said delay means for achieving a delay equivalent to the determined difference, shift register means having a plurality of binary bit positions with each position representing one of said plurality of delay means, said third device includes a surface comprising a magnetic material, and a plurality of transducer means for writing information into and reading information from said surface, each of said delay means being separated by a transducer means, said means for determining comprises means for subtracting said addresses and for storing the difference in a binary form or logical ones or zeros, as the case of inputs from the plurality of transducer means for 10 reading, including an input from said first device, said plurality of inputs to said matrices decreasing as a function of the increased delay between transducers, each of said matrices having a single output to a selected one of said means for writing, as a function of the logical states of said inputs,

said outputs sequentially are connected to the transducer associated with the smallest of said delays and continuing to the transducer associated with the means for determining the difl'erence between an address in the first memory device and an address in the second memory device,

said third device comprises a plurality of delay means for delaying data received from the first device until it is transferred to the second device, including means responsive to said means for determining the diiference for by-passing certain of said delay means for achieving a delay equivalent to the determined difference,

means interposed between said first and seocnd devices comprising means for examining said difference and for delaying information transferred between said first and second devices a period of time equivalent to the electronic delays indicated by said difierenoe.

References Cited UNITED STATES PATENTS largest delay, including an output connected to the 20 2,674,732 4/ 1954 Robbins 340-347 second device. 2,674,733 4/1954 Robbins 340347 4. A variable delay system for transferring data from 2,907,004 9/1959 Chien et a], 340-174 a first non-random access memory device to a second 3,302,176 1/1967 McLaughlin 340172.$

non-random access memory device comprising,

a third non-random access memory device connected 25 RAULFE B. ZACHE, Primary Examiner between the first and second devices, 

